The invention relates generally to node processors for low density parity check decoders.
Low density parity check (LDPC) codes are a class of linear error correction codes (ECCs) that can be decoded efficiently with iterative decoders. The decoders can be represented by Tanner graphs, in which variable nodes that correspond to code word symbols, or vectors of symbols, and parity constraint nodes that correspond to parity constraints are interconnected by edges that represent the inclusion of the code word symbols in the respective parity constraints. The LDPC codes can be referred to by variable node degree distributions, which relate to the number of edges connecting to the respective variable nodes. For example, a code may have a variable node degree distribution in which x percent of the variable nodes are degree three and 100−x percent are degree four. The degrees of the respective variable nodes in the example indicate that corresponding code word symbols are associated with three or four parity constraints. An LDPC code has a higher variable node degree distribution if it has a larger number of higher degree variable nodes.
The parity constraint nodes are also denoted by degrees, which indicate the number of code word symbols that are included in associated parity check equations. The LDPC code could instead be represented by a parity check H matrix.
When contrasted with other linear ECCs, such as Reed Solomon codes, the LDPC codes have good dB performance, that is, perform well in low signal-to-noise situations. However, the LDPCs also have relatively high error floors, or sector failure rates, that remain relatively constant even at higher signal-to-noise ratios. In the channels of interest, error floors are lower for LDPC codes that have higher degree variable nodes. There is thus a trade off involve in optimizing either for better dB performance or lower error floors. Generally, data storage systems must meet prescribed sector failure rate minimums, and the LDPC codes are selected based on their error floors. The same trade off occurs with respect to the burst error correction capabilities of the LDPC codes.
A solution to this tradeoff is a decoding system comprising an iterative decoder that is characterized by a plurality of variable nodes and a plurality of parity constraint nodes, and a processor that at respective iterations disables one or more selected parity constraint nodes to operate the iterative decoder with a selected variable node degree distribution code and at other iterations enables one or more of the selected parity constraint nodes to operate the iterative decoder with one or more higher variable node degree distribution codes, which is described in co-pending U.S. patent application Ser. No. 12/185,437 filed Aug. 4, 2008 entitled Low Density Parity Check Decoder Using Multiple Variable Node Degree Distribution Codes, which is assigned to a common Assignee and incorporated herein in its entirety by reference. The decoder works well and may operate with various codes that utilize different degree parity constraint nodes.